DESE announces two open RISC-V cores

Department of Electronic Systems Engineering (DESE), EECS, IISc has shared two Softcore Processor IPs developed at DESE. These are developed by the Reconfigurable Computing Lab of DESE. First one is a 32-bit RISC-V Processor, and the second a 32-bit RISC-V Vector Processor. These are targeted to FPGAs and can be modified for ASIC implementation. The link for these IP’s are below: