Revised Intake: 30

GATE Cut-off: Roughly around 500 top rank holders will be called for written/interview.

Selection Process: Applicants must have to apply formally for this M-Tech program to become eligible for admissions. After screening based on the GATE score, applicants will be called for an aptitude test and interview, which will be conducted during April 23 and 25, 2019. The number of students to be called will be approximately 15 times the number of seats. This will determine the GATE cut off scores. Only those who clear the written test will be called for interviews. Final selection will be based on GATE and performance in the aptitude test and interview.

Written Test: The question paper for the written test is set for the duration of 1 hour and 30 minutes (on April  23rd 2019, 10:45 AM – 12:45 PM, in the Central Lecture Hall). Questions will be mostly from the GATE ECE syllabus, having a focus on Digital/Analog circuits, Semiconductor devices & its physics, Mathematics, etc. Written test will be subjective in nature and will be designed to test your (i) real-world problem-solving ability, (ii) approach to analyze & solve engineering problems, (iii) general aptitude and (iv) scientific aptitude.

Interview: Only those who clear the written test will be called for interviews on April 24th & 25th, 2019.

Qualification and Eligibility: BE/ B Tech or equivalent degree with a GATE Paper in EE; EC; CS and IN.

Areas of Specialized Study: Semiconductor Devices and Technology; Nanoelectronics Devices; Microelectronics Lab; Physics and Design of Transistors; Carrier Transport in Nanoelectronics Devices; Digital VLSI Circuit; Analog VLSI Circuits; Semiconductor Device Modelling; Optoelectronic Devices; Design of Power Semiconductor Devices; Reliability of Nanoscale Circuits and Systems; RF IC and Systems; Photonics Integrated Circuits and Digital Systems Design with FPGAs

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Note: M-Tech in “Microelectronic Systems” has been renamed to “Microelectronics and VLSI Design”

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